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ATmega128
Figure 142. Parallel Programming Timing, Loading Sequence with Timing Requirements
LOAD ADDRESS
(LOW BYTE)
LOAD DATA
(LOW BYTE)
LOAD DATA
(HIGH BYTE)
LOAD DATA
LOAD ADDRESS
(LOW BYTE)
XTAL1
BS1
PAGEL
t XLXH
t XLPH
t PLXH
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
XA0
XA1
Note:
The timing requirements shown in Figure 141 (i.e. t DVXH , t XHXL , and t XLDX ) also apply to loading
operation.
Figure 143. Parallel Programming Timing, Reading Sequence ( W ithin the Same Page) with
Timing Requirements
LOAD ADDRESS
(LOW BYTE)
READ DATA
(LOW BYTE)
READ DATA
(HIGH BYTE)
LOAD ADDRESS
(LOW BYTE)
t XLOL
XTAL1
t BHDV
BS1
t OLDV
OE
t OHDZ
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
XA0
XA1
Note:
The timing requirements shown in Figure 141 (i.e. t DVXH , t XHXL , and t XLDX ) also apply to reading
operation.
Table 126. Parallel Programming Characteristics, V CC = 5 V ±10%
Symbol
V PP
Parameter
Programming Enable Voltage
Min
11.5
Typ
Max
12.5
Units
V
I PP
t DVXH
t XLXH
t XHXL
t XLDX
t XL W L
Programming Enable Current
Data and Control Valid before XTAL1 High
XTAL1 Low to XTAL1 High
XTAL1 Pulse W idth High
Data and Control Hold after XTAL1 Low
XTAL1 Low to W R Low
67
200
150
67
0
250
μ A
ns
ns
ns
ns
ns
299
2467X–AVR–06/11
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